1. Field of the Invention
The invention relates generally to a method of manufacturing a flash memory device and, in particular, to a method of manufacturing a NAND flash memory device, in which when forming spacers on sidewalls of selection gates, damage to a semiconductor substrate between edge cell gates and the selection gates can be prevented.
2. Discussion of Related Art
A NAND flash memory device includes a number of cell blocks. Each of the cell blocks includes a plurality of cell strings, each of which having a plurality of cells for storing data connected in series. A drain selection line and a source selection line are formed between the cell string and the drain, and between the cell string and a common source.
The cell string, the source selection line, and the drain selection line are orthogonal to an isolation film formed to define an active region and a field region, and are spaced apart one another in parallel by a predetermined distance.
Furthermore, the cell includes a cell gate in which a tunnel oxide film, a floating gate, a dielectric layer, and a control gate are stacked, and an impurity region formed on a semiconductor substrate at both sides of the cell gate.
Meanwhile, a select transistor is formed at the intersection of the selection line and the active region. The selection gate of the select transistor may be formed using the same process as the cell gate formation process or may be formed by stripping the dielectric layer in the cell gate formation process.
Cell gates forming one string are formed to have the same width and distance. In the case where two cell gates adjacent to the selection gate (for example, 32 cells) form one string, however, the distance between cell gates connected to a first word line and a last word line (for convenience sake, “edge cell gates”) and adjacent cell gates is the same as the distance between other cell gates, but the distance between the cell gates connected to the first word line and the last word line and the selection gate is wider than the distance between other cell gates.
Meanwhile, the distance between the selection gates is wider than that between the cell gates, and is also wider than that between the edge cell gate and the selection gate.
If the distance between the cell gates is narrower than the distance between the selection gates and the distance between the edge cell gate and the selection gate is wider than the distance between the cell gates as described above, the between-the-cell gates are fully buried, but the between-the-edge cell gate and the selection gate are not fully buried when forming an oxide film on the entire structure in order to form spacers on sidewalls of the selection gate.
As a result, in the process of blanket-etching the nitride film to form the spacers on the sidewalls of the selection gate, the semiconductor substrate between the edge cell gate and the selection gate is etched and damaged accordingly.